1. Field of the Invention
The present invention relates to a semiconductor memory apparatus which can perform a reading operation at a high speed.
2. Description of the Related Art
Recently, there have been a large amount of demands with respect to LSI (ASIC) for specified uses. A maker for manufacturing LSIs has been developing a compile system for preparing functional blocks constituting a memory in advance and synthesizing the functional blocks by software so as to rapidly correspond to various requirements of users with respect to ASIC.
However, in the memory of the above-mentioned compile system, a delay time for securing a sufficient precharging operation cannot be fixed to a minimum value since a user designates the construction of bits and words. When a variable delay time is set by a combination of resistors and capacitors, the delay time is set to be large by 10 to 100% to secure the operations thereof in consideration of a dispersion in process, a change in temperature, etc. An access time is increased by this margin of the delay time.
In a circuit for generating an internal clock signal, with respect to a pulse of a SAT signal transmitted from this generating circuit, a time difference in rise between a pulse of a supplied ATD signal and the pulse of the SAT signal is determined by the relation between the ability of a PMOS transistor as a load transistor, a capacitor on an output line, and the ability of NMOS transistors as a drive transistor. On the other hand, a time difference in fall between the ATD signal and the SAT signal is determined by the relation between the ability of the PMOS transistor and the capacitor on the output line. To prepare the operations of the respective circuit elements for the next operating cycle, it is necessary to reduce the fall of the SAT signal, i.e., the fall time difference.
However, in the above circuit, both the rise time difference and the fall time difference cannot be decreased, thereby preventing the memory from being operated at a high speed. Further, when the fall time difference is decreased, the consumed amount of an electric current is increased and therefore the consumed amount thereof cannot be reduced.
In the internal clock signal generating circuit, the delay time is increased since the ATD signal is transmitted through many circuit elements so that the memory cannot be also operated at a high speed.